Книга: Murra Subba Reddy «Low Power Flash ADC»
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Производитель: "LAP Lambert Academic Publishing" In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1. 2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC. ISBN:9783845440842 Издательство: "LAP Lambert Academic Publishing" (2011)
ISBN: 9783845440842 |
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